RT8876A
triggered. When quick response is triggered, the quick
response circuit will generate a quick response pulse.
The internal quick response pulse generation circuit is
similar to the on-time generation circuit. The only
difference is the QRSET pin. The voltage at the QRSET
pin also influences the pulse width of quick response. A
voltage divider circuit is recommended to be applied to
the QRSET pin. Therefore, with a little modification of
equation (12), the pulse width of quick response pulse
can be calculated as :
Current Mirror
FB
+
-
V
CC_SENSE
R
IMONFB
IMONFB
IMON
I
Mirror
R
IMON
Figure 15. CORE VR : Current Monitoring Circuit
The ADC circuit of the CORE VR monitors the voltage
variation at the IMONpin from 0V to 3.3V, and this voltage
is decoded into digital format and stored into
Output_Current register. The ADC divides 3.3V into 255
levels, so LSB = 3.3V/255 = 12.941mV. Platform designers
should design VIMON to be 3.3V at ICCMAX. For example,
when load current = 50% x ICCMAX, VIMON = 1.65V and
Output_Current register = 7Fh. The IMONpin is an output
of the internal operational amplifier and sends out IMON
signal. When the data of Output_Current register reaches
255d (when IMONvoltage rises above 3.3V), theALERT
signal will be asserted to low, which is so-called SVID
ICCMAX alert. In the mean time, the CORE VR will assert
the bit 2 data to 1 in Status_1 register. The ALERT
assertion will be de-asserted when the data of
Output_Current register decreases to 242d (when IMON
voltage falls under 3.144V). The bit 2 assertion of Status_1
register is latched and can only be cleared when two criteria
are met : the data of Output_Current register decreases
to 242d (when IMON voltage falls under 3.144V) and the
GetReg command is sent to the Status_1 register of the
CORE VR.
VQRSET
tON, QR
=
× tON
1.2
20.33×10−12 ×RTON × VQRSET
=
(23)
VIN − VDAC
After generating a quick response pulse, the pulse is then
applied to the on-time generation circuit, and all the active
phases on-times will be overridden by the quick response
pulse.
Current Mirror
VDAC
+
-
QR trigger
R
IMONFB
IMONFB
I
Mirror
V
CC_SENSE
Figure 16. CORE VR : Quick Response Triggering
Circuit
Over Current Protection
The CORE VR compares a programmable current limit
set point to the voltage from the current sense amplifier
output of each phase for Over Current Protection (OCP).
Therefore, the OCP mechanism of the RT8876A
implements per-phase current protections. The voltage
applied to the OCSET pin defines the desired current limit
Quick Response
The CORE VR utilizes a quick response feature to support
heavy load current demand during instantaneous load
transient. The CORE VR monitors the current of the
IMONFB pin, and this current is mirrored to internal quick
response circuit. At steady state, this mirrored current
will not trigger a quick response. When the VOUT, CORE
voltage drops abruptly due to load apply transient, the
mirrored current flowing into quick response circuit will
also increase instantaneously. When the mirrored current
instantaneously rises above 5μA, quick response will be
threshold, ILIMIT_CORE
:
VOCSET = 48 x ILIMIT_CORE x RSENSE
(24)
Connect a resistive voltage divider from VCC5 to GND,
and the joint of the resistive voltage divider is connected
to the OCSET pin as shown in Figure 17. For a given
ROC2
,
V
⎛
⎞
CC5
(25)
R
= R
×
OC2
−1
⎟
OC1
⎜
⎝
V
OCSET
⎠
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
38
DS8876A-02 October 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
