RX62Nグループ、RX621グループ
5. Electrical Characteristics
Table 5.15
Timing of On-Chip Peripheral Modules (3)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V
PCLK = 8 to 50MHz
Ta = -40 to +85C
Item
Symbol
tOH
Min.
Max.
Unit
ns
Test Conditions
RSPI
Data output hold time
Master
Slave
0
—
Figure 5.39 to Figure
5.42
0
—
Sucessive transmission
delay time
Master
tTD
tSPcyc+2 × tPcyc 8 × tSPcyc ns
+2 × tPcyc
Slave
4 × tPcyc
—
—
5
MOSI, MISO rise/fall time
Output
tDr,
tDf
ns
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
Output
—
10
[100-pin LQFP/
85-pin TFLGA]
Input
—
—
1
5
µs
ns
SSL rise/fall time
Output
tSSLr,
tSSLf
[176-pin LFBGA
145-pin TFLGA
144-pin LQFP]
Output
—
10
[100-pin LQFP/
85-pin TFLGA]
Input
—
—
—
1
4
3
µs
Slave access time
tSA
tPcyc
tPcyc
Figure 5.41 and Figure
5.42
Slave output release tim
tREL
Note 1. tPcyc: PCLK cycle
R01UH0033JJ0110 Rev.1.10
2010.12.24
Page 116 of 1931
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