RX62Nグループ、RX621グループ
5. Electrical Characteristics
Table 5.13
Timing of On-Chip Peripheral Modules (1) (1/2)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V
PCLK = 8 to 50MHz
Ta = -40 to +85C
Item
SCI
Symbol
tScyc
Min.
Max.
—
Unit
ns
Test Conditions
4 × tPcyc
Input clock cycle
Asynchronous
Figure 5.34 and
Figure 5.35
6 × tPcyc
—
Clock
synchronous
0.4 × tScyc
—
0.6 × tScyc
ns
ns
ns
ns
Input clock pulse width
Input clock rise time
Input clock fall time
Output clock cycle
tSCKW
tSCKr
tSCKf
tScyc
20
20
—
—
—
4 × tPcyc
6 × tPcyc
Asynchronous
Clock
synchronous
0.4 × tScyc
0.6 × tScyc
ns
ns
ns
Output clock pulse width
Output clock rise time
Output clock fall time
tSCKW
tSCKr
tSCKf
tTXD
—
—
20
20
Transmit data delay time
(clock synchronous)
—
40
40
25
25
40
—
—
—
—
ns
ns
ns
ns
ns
Receive data setup time
(clock synchronous)
tRXS
Receive data hold time
(clock synchronous)
tRXH
A/D
10-bit A/D converter
trigger input setup time
tTRGS
Figure 5.36
converter
12-bit A/D converter
tTRGS
trigger input setup time
R01UH0033JJ0110 Rev.1.10
2010.12.24
Page 113 of 1931
RENESAS [ RENESAS TECHNOLOGY CORP ]
