RX62Nグループ、RX621グループ
5. Electrical Characteristics
Table 5.14
Timing of On-Chip Peripheral Modules (2) (2/2)
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V
PCLK = 8 to 50MHz
Ta = -40 to +85C
Item
Symbol
tSU
Min.
16
Max.
—
Unit
ns
Test Conditions
RSPI
Data input setup time
Master
Figure 5.39 to Figure
5.42
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
Master
[100-pin LQFP/
85-pin TFLGA]
30
—
—
Slave
20-2 × tPcyc
Data input hold time
SSL setup time
Master
Slave
tH
0
—
—
ns
20+2 × tPcyc
Master
Slave
tLEAD
1
8
tSPcyc
tPcyc
tSPcyc
tPcyc
ns
4
—
8
SSL hold time
Master
Slave
tLAG
1
4
—
20
Data output delay time
Master
tOD
—
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
Master
[100-pin LQFP/
85-pin TFLGA]
—
—
30
Slave
3 × tPcyc+40
[176-pin LFBGA/
145-pin TFLGA/
144-pin LQFP]
Slave
—
3 × tPcyc+50
[100-pin LQFP/
85-pin TFLGA]
Note 1. tPcyc: PCLK cycle
R01UH0033JJ0110 Rev.1.10
2010.12.24
Page 115 of 1931
RENESAS [ RENESAS TECHNOLOGY CORP ]
