RX62Nグループ、RX621グループ
5. Electrical Characteristics
5.3.4
EXDMAC Timing
Table 5.12
EXDMAC Timing
Conditions: VCC = PLLVCC = AVCC = VCC_USB = 2.7 to 3.6V, VREFH = 2.7V to AVCC
VSS = PLLVSS = AVSS = VREFL = VSS_USB = 0V
ICLK = 8 to 100MHz, PCLK = 8 to 50MHz, BCLK = 8 to 100MHz, SDCLK = 8 to 50MHz
Ta = -40 to +85C
Item
Symbol
tEDRQS
Min.
20
Max.
—
Unit
ns
Test Conditions
Figure 5.22
EXDMAC
EDREQ setup time
EDREQ hold time
EDACK delay time
tEDRQH
tEDACD
5
—
ns
ns
—
15
Figure 5.23 and Figure 5.24
BCLK
tEDRQS tEDRQH
EDREQ0
EDREQ1
Figure 5.22 EDREQ0 and EDREQ1 Input Timing
BCLK
tEDACD
tEDACD
EDACK0
EDACK1
Figure 5.23 EDACK0 and EDACK1 Single-Address Transfer Timing (for a CS Area)
BCLK
tEDACD
tEDACD
EDACK0
EDACK1
Figure 5.24 EDACK0 and EDACK1 Single-Address Transfer Timing (for SDRAM)
R01UH0033JJ0110 Rev.1.10
2010.12.24
Page 111 of 1931
RENESAS [ RENESAS TECHNOLOGY CORP ]
