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R5F21134DFP 参数 Datasheet PDF下载

R5F21134DFP图片预览
型号: R5F21134DFP
PDF下载: 下载PDF文件 查看货源
内容描述: 16位单片机M16C族/ R8C / Tiny系列 [16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY/R8C/Tiny SERIES]
分类和应用: 微控制器和处理器外围集成电路计算机时钟
文件页数/大小: 224 页 / 2076 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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R8C/13 Group  
13.2 Clock Asynchronous Serial I/O (UART) Mode  
Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)  
Tc  
Transfer clock  
1”  
0”  
UiC1 register  
TE bit  
Write data to UiTB register  
1”  
0”  
UiC1 register  
TI bit  
Transferred from UiTB register to UARTi transmit register  
Stopped pulsing  
because the TE bit  
= 0”  
Start  
bit  
ParityStop  
bit bit  
ST  
TxDi  
D0  
D1  
ST  
D0  
D3  
D7  
ST  
D0  
D3  
D7  
D1  
D2  
D4  
D5  
D6  
P
SP  
D1  
D2  
D4  
D5  
D6  
P SP  
UiC0 register  
TXEPT bit  
1”  
0”  
1”  
0”  
SiTIC register  
IR bit  
Set to 0when interrupt request is accepted, or set by a program  
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT  
The above timing diagram applies to the case where the register bits  
are set as follows:  
UiMR register PRYE bit = 1 (parity enabled)  
UiMR register STPS bit = 0 (1 stop bit)  
fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO  
EXT: frequency of UiBRG count source (external clock)  
n: value set to UiBRG  
i: 0, 1  
)
f
UiIRS bit = 1 (an interrupt request occurs when transmit completed):  
Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)  
Tc  
Transfer clock  
1”  
0”  
1”  
UiC1 register  
TE bit  
Write data to UiTB register  
UiC1 register  
TI bit  
0”  
Transferred from UiTB register to UARTi  
transmit register  
Stop Stop  
bit bit  
Start  
bit  
TxDi  
ST  
ST  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
8
SPSP ST  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
D
8
SPSP  
D0  
D1  
1”  
0”  
UiC0 register  
TXEPT bit  
SiRIC register  
IR bit  
1”  
0”  
Set to 0when interrupt request is accepted, or set by a program  
The above timing diagram applies to the case where the register  
bits are set as follows:  
UiMR register PRYE bit = 0 (parity disabled)  
UiMR register STPS bit = 1 (2 stop bits)  
UiIRS bit = 0 (an interrupt request occurs when transmit buffer  
becomes empty)  
Tc = 16 (n + 1) / fj or 16 (n + 1) / fEXT  
fj: frequency of UiBRG count source (f1SIO, f8SIO, f32SIO  
EXT: frequency of UiBRG count source (external clock)  
n: value set to UiBRG  
i: 0, 1  
)
f
Figure 13.9 Transmit Operation  
Rev.1.20 Jan 27, 2006 page 121 of 205  
REJ09B0111-0120  
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