R8C/13 Group
13.2 Clock Asynchronous Serial I/O (UART) Mode
13.2.3 Bit Rate
Divided-by-16 of frequency by the UiBRG (i=0 to 1) register in UART mode is a bit rate.
<UART Mode>
• When selecting internal clock
fj
Setting value to the UiBRG register =
–1
Bit Rate ✕ 16
fj : Count source frequency of the UiBRG register (f1SIO, f8SIO and f32SIO)
• When selecting external clock
fEXT
Setting value to the UiBRG register =
–1
Bit Rate ✕ 16
fEXT : Count source frequency of the UiBRG register (external clock)
Figure 13.11 Calculation Formula of UiBRG (i=0 to 1) Register Setting Value
Table 13.7 Bit Rate Setting Example in UART Mode
Bit Rate
(bps)
BRG
System Clock = 20MHz
System Clock = 8MHz
Count Source BRG Setting Value Actual Time(bps) Error(%) BRG Setting Value Actual Time(bps) Error(%)
1200
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
129 (8116)
64 (4016)
32 (2016)
129 (8116)
86 (5616)
64 (4016)
42 (2A16)
39 (2716)
32 (2016)
23 (1716)
1201.92
2403.85
0.16
0.16
51 (3316)
25 (1916)
12 (0C16)
51 (3316)
34 (2216)
25 (1916)
16 (1016)
15 (0F16)
12 (0C16)
9 (0916)
1201.92
2403.85
0.16
0.16
0.16
0.16
–0.79
0.16
2.12
0.00
0.16
–2.34
2400
4800
4734.85
–1.36
0.16
4807.69
9600
9615.38
9615.38
14400
19200
28800
31250
38400
51200
14367.82
19230.77
29069.77
31250.00
37878.79
52083.33
–0.22
0.16
14285.71
19230.77
29411.76
31250.00
38461.54
50000.00
0.94
0.00
–1.36
1.73
Rev.1.20 Jan 27, 2006 page 123 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
