R8C/13 Group
13.1 Clock Synchronous Serial I/O Mode
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
“1”
“0”
U0C1 register
TE bit
Write data to U0TB register
U0C1 register
TI bit
“1”
“0”
Transferred from U0TB register to UART0 transmit register
T
CLK
Stopped pulsing because the TE bit = 0
CLK
0
TxD0
D7
D7
D7
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
D0
D1
D2
D3
D4
D5
D6
U0C0 register
TXEPT bit
“1”
“0”
S0TIC register
IR bit
“1”
“0”
Set to “0” when interrupt request is accepted, or set by a program
Tc = TCLK = 2(n + 1) / fi
fi: frequency of U0BRG count source (f1SIO, f8SIO, f32SIO
n: value set to U0BRG register
)
The above timing diagram applies to the case where the register bits are set as follows:
• U0MR register CKDIR bit = 0 (internal clock)
• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
• U0IRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
• Example of receive timing (when external clock is selected)
“1”
U0C1 register
RE bit
“0”
“1”
U0C1 register
TE bit
“0”
Write dummy data to U0TB register
“1”
“0”
U0C1 register
TI bit
Transferred from U0TB register to UART0 transmit register
1 / fEXT
CLK0
RxD0
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Read out from U0RB register
Transferred from UART0 receive register
to U0RB register
“1”
“0”
U0C1 register
RI bit
“1”
“0”
S0RIC register
IR bit
Set to “0” when interrupt request is accepted, or set by a program
The above timing diagram applies to the case where the register bits are set as follows:
• U0MR register CKDIR bit = 1 (external clock)
• U0C0 register CKPOL bit = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
Make sure the following conditions are met when input to the CLK0 pin before receiving data is high:
• U0C1 register TE bit = 1 (transmit enabled)
• U0C1 register RE bit = 1 (receive enabled)
• Write dummy data to the U0TB register
fEXT: frequency of external clock
Figure 13.6 Transmit and Receive Operation
Rev.1.20 Jan 27, 2006 page 116 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
