R8C/13 Group
13.1 Clock Synchronous Serial I/O Mode
Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
U0TB
Bit
0 to 7
Function
Set transmission data
U0RB
0 to 7
Reception data can be read
Overrun error flag
OER
U0BRG
U0MR
0 to 7
Set a bit rate
SMD2 to SMD0
CKDIR
CLK1 to CLK0
TXEPT
NCH
Set to “0012”
Select the internal clock or external clock
Select the count source for the U0BRG register
Transmit register empty flag
Select TxD0 pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
U0C0
CKPOL
UFORM
TE
U0C1
TI
RE
Set this bit to “1” to enable reception
Reception complete flag
RI
UCON
U0IRS
U0RRM
TXDISEL
TXDIEN
Select the source of UART0 transmit interrupt
Set this bit to “1” to use continuous receive mode
Set to “0”
Set to “0”
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
Table 13.3 lists the functions of the I/O pins during clock synchronous serial I/O mode. Note that for a
period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs an
“H”. (If the NCH bit is set to “1”(N-channel open-drain output), this pin is in high-impedance state.)
Table 13.3 Pin Functions
Pin name
TxD
Function
Method of selection
0
Serial data output
(Outputs dummy data when performing reception only)
(P1
4)
Serial data input
RxD
0
)
PD1 register PD1_5 bit=0
(P15 can be used as an input port when performing transmission only)
(P1
5
CLK
(P16)
0
Transfer clock output
Transfer clock input
U0MR register CKDIR bit=0
U0MR register CKDIR bit=1
PD1 register PD1_6 bit=0
Rev.1.20 Jan 27, 2006 page 115 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
