MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Receive
TXD0
Receive starts when bit 2 (REk flag) of UARTk Transmit/Receive
CLKS1
CLKS0
CLK0
control register 1 is set to “1”.
____
UART0
The RTSk output is “H” when the REk flag is “0” and goes “L” when
the REk flag changed to “1” and the TIk flag did to “0”. It goes back to
“H” when receive starts. The TIk flag is cleared to “0” by write dummy
____
data to the transmit buffer register. It is ready to receive when RTSk
DIN
DIN
DIN
output is “L”.
CLK
CLK
CLK
The data from the RxDk pin is retrieved and the contents of the re-
ceive register is shifted by 1 bit each time when the transmission
clock CLKj changes from “L” to “H.” When an 8-bit data is received,
Note: This is available in clock synchronous serial I/O, using internal clock
and transmission mode.
the contents of the receive register is transferred to the receive buffer
register and bit 3 (RIk flag) of UARTk Transmit/Receive control reg-
ister 1 is set to “1”. In other words, the setting “1” to the RIk flag indi-
cates that the receive buffer register contains the received data.
When the RIk flag changes from “0” to “1”, the interrupt request bit in
the UARTk receive interrupt control register is set to “1”. Bit 4 (OERk
flag) of UARTk Transmit/Receive control register 1 is set to “1” when
the next data is transferred from the receive register to the receive
buffer register while RIk flag is “1”, and indicates that the next data
was transferred to the receive register before the contents of the re-
ceive buffer register was read. RIk flag is automatically cleared to “0”
when the low-order byte of the receive buffer register is read or when
the REk flag is cleared to “0”. The OERk flag is cleared when the REk
flag is cleared or port P8 is set to a parallel port. Bit 5 (FERk flag), bit
6 (PERk flag), and bit 7 (SUMk flag) are ignored in clock synchro-
nous mode.
Fig. 61 External connection example in plural output of transmit
clock mode
7
0
6
5
4
3
0
2
0
1
0
0
1
Address
UART0 Transmit/Receive mode register 3016
0 0 1 : Clock synchronous
0
: Internal clock
This bit must be “0”
7
7
6
6
6
5
5
5
4
1
3
3
3
2
1
1
1
0
0
0
Address
3416
UART0 Transmit/Receive control register 0
1
: Disable CTS, RTS
When reading the contents of the receive buffer register, the received
data is pulled from the least significant bit (LSB) in the received order
if bit 7 (TEM) of the UARTj Transmit/Receive control registers 0 is “0”.
If bit 7 (TEM) is “1”, the received data is pulled from the most signifi-
cant bit (MSB).
4
4
2
0
Address
3516
UART0 Transmit/Receive control register 1
: Disable receive
0
As shown in Figure 54, with clock synchronous serial communica-
tion, data cannot be received unless the transmitter is operating be-
cause the receive clock is created from the transmission clock.
Therefore, the transmitter must be operating even when there is no
need to sent data from UARTk to UARTj.
7
0
2
Address
A-D control register 1 1F16
0
: Disable D-A output
Fig. 62 Other registers except special function select register 1 bit
configuration in plural output of transmit clock mode
Table 6. Output pin of transmit clock select bits and pins’ function
Output pin of trans-
Pin name
mit clock select bits
____ ____
TC1
0
TC0
0
P81/CLK0 P82/RXD0 P80/CTS0/RTS0/DA0
____ ____
CLK0
CLK0
“H”
RXD0
P80/CTS0/RTS0/DA0
0
1
“H” (Note)
CLKS2
P80
P80
1
0
1
1
“H”
“H” (Note)
CLKS1
Note:It outputs “H” when bit 2 of the port P8 direction register is “1”, and it
becomes floating when bit 2 is “0”.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
