MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(UART) serial I/O port using start and stop bits.
SERIAL I/O PORTS
Figures 56 and 57 show the connections of receiver/transmitter ac-
cording to the mode.
Two independent serial I/O ports are provided. Figure 54 shows a
block diagram of the serial I/O ports.
Figure 58 shows the bit configuration of the UARTi Transmit/Receive
control register.
Bits 0, 1, and 2 of the UARTi(i = 0,1) Transmit/Receive mode register
shown in Figure 55 are used to determine whether to use port P8 as
parallel port, clock synchronous serial I/O port, or asynchronous
Each communication method is described below.
Data bus(odd)
Data bus(even)
Bit converter
0
0
0
0
0
0
0 D8 D7 D6 D5 D4 D3 D2 D1 D0 Receive buffer register
UART0(3716,3616)
UART1(3F16,3E16)
RXDi
Receive register
Receive clock
UART receive
Receive
control
circuit
1/16 Divider
Bit rate
generator
Clock synchronous
UART transmission
UART0(3116)
UART1(3916)
Internal
Clock source selection
Transmission clock
1/16 Divider
Transmission
control circuit
Pf2
Clock synchronous
Pf16
Pf64
Pf512
Clock synchronous
TXDi
1/(n + 1)
Divider
(Internal clock)
Transmit register
1/2 Divider
External Clock synchronous
(Internal clock)
Clock synchronous
(External clock)
CLKi
Transmit
buffer register
D8 D7 D6 D5 D4 D3 D2 D1 D0
UART0(3316,3216)
UART1(3B16,3A16)
CTSi/RTSi
Data bus
(odd)
Bit converter
Data bus(even)
Fig. 54 Serial I/O port block diagram
Addresses
3016
3816
7
6 5 4 3 2 1 0
UART 0 Transmit/Receive mode register
UART 1 Transmit/Receive mode register
Serial I/O mode select bit
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal/External clock select bit
0 : Internal clock
1 : External clock
Stop bit length select bit
0 : 1 stop bit
1 : 2 stop bits
Even/Odd parity select bit
0 : Odd parity
1 : Even parity
Parity enable select bit
0 : No parity
1 : With parity
Sleep select bit
0 : No sleep
1 : Sleep
Fig. 55 UARTi Transmit/Receive mode register bit configuration
46