MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Data bus(odd)
Data bus(even)
Bit Converter
Receive buffer register
0
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
8bit
9bit
2 stop bit
Parity
7bit
8bit
9bit
9 bit
Synchronous
7 bit
RXDi
Stop
bit
Stop
bit
Parity
bit
No
parity
Receive register
1 stop bit
7bit
8bit
Synchronous
Synchronous
Fig. 56 Receiver block diagram
Data bus(odd)
Data bus(even)
Bit Converter
Transmit buffer register
D8
D7
D6
D5
D4
D3
D2
D1
D0
7bit
8bit
9bit
Synchronous
9bit
Synchr-
onous
2 stop bit
Parity 7bit
8bit
Parity
bit
TXDi
9bit
Stop
Stop
bit
“0”
bit
No
parity
8 bit
7 bit
Transmit register
1 stop bit
“0”
Synchronous
Fig. 57 Transmitter block diagram
Addresses
7
6
5
4
3
2
X
1
0
UART 0 Transmit/Receive control register 0 3416
UART 1 Transmit/Receive control register 0 3C16
MSB/
LSB
T
R/C TCS1 TCS0
EPTY
BRG count source select bit
0 0 : Select Pf
2
0 1 : Select Pf16
1 0 : Select Pf64
1 1 : Select Pf512
CTS, RTS select bit
0 : Select CTS
1 : Select RTS
Transmit register empty bit
CTS, RTS enable bit
0 : Enable CTS, RTS
1 : Disable CTS, RTS (Input/Output port)
Transfer format select bit (Note)
0 : LSB first
Note : This bit is valid in clock synchronous mode.
Fix this bit to “0” in UART mode.
1 : MSB first
Addresses
7
6
5
4
3
2
1
0
UART 0 Transmit/Receive control register 1 3516
UART 1 Transmit/Receive control register 1 3D16
SUM PER FER OER RI
RE
TI
TE
Transmit enable flag
Transmit buffer empty flag
Receive enable flag
Receive complete flag
Overrun error flag
Framing error flag
Parity error flag
Error sum flag
Fig. 58 UARTi Transmit/Receive control register bit configuration
47
RENESAS [ RENESAS TECHNOLOGY CORP ]
