MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bit 5 is a select bit of odd parity or even parity.
ASYNCHRONOUS
In the odd parity mode, the parity bit is adjusted so that the sum of 1s
SERIAL COMMUNICATION
in the data and parity bit is always odd.
Asynchronous serial communication can be performed using 7-, 8-,
or 9-bit length data. The operation is the same for all data lengths.
The following is the description for 8-bit asynchronous communica-
tion.
In the even parity mode, the parity bit is adjusted so that the sum of
the 1s in the data and parity bit is always even.
Bit 6 is the parity bit select bit which indicates whether to add parity
bit or not.
With 8-bit asynchronous communication, bit 0 of UARTi Transmit/
Receive mode register is “1”, bit 1 is “0”, and bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3 is
“0”, an internal clock is selected and if bit 3 is “1”, then external clock
is selected. If an internal clock is selected, bit 0 (TCS0) and bit 1
(TCS1) of UARTi Transmit/Receive control register 0 are used to se-
lect the clock source. When an internal clock is selected for asyn-
chronous serial communication, the CLKi pin can be used as a
normal I/O pin.
Bits 4 to 6 must be set or reset according to the data format used in
the communicating devices.
Bit 7 is the sleep select bit. The sleep mode is described later.
The UARTi Transmit/Receive control register 0 bit 2 is used to deter-
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mine whether to use CTSi input or RTSi output.
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CTSi input is used if bit 2 is “0” and RTSi output is used if bit 2 is “1”.
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If CTSi input is selected, the user can control whether to stop or start
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transmission by external CTSi input.
Bit 4 of the UART Transmit/Receive control register 0 is used to de-
The selected internal or external clock is divided by (n+1), then by
16, and is passed through a control circuit to create the UART trans-
mission clock or UART receive clock.
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termine whether to use CTS or RTS signal. Bit 4 must be “0” when
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CTS or RTS signal is used. Bit 4 must be “1” when CTS or RTS sig-
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nal is not used. When CTS or RTS signal is not used, CTS/RTS pin
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Therefore, the transmission speed can be changed by changing the
contents (n) of the bit rate generator. If the selected clock is an inter-
nal clock Pfi or an external clock fEXT,
can be used as a normal port. The case using CTS and RTS signals
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are explained below. However, when CTS and RTS signals are not
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used, there are no condition of CTSi input, and there is no RTSi out-
put.
Bit Rate = (Pfi or fEXT) / {(n+1)×16}
Clear UARTj Transmit/Receive control register 0 bit 7 to “1” in asyn-
chronous communication.
Bit 4 is the stop bit length select bit to select 1 stop bit or 2 stop bits.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
