MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
transmission clock CLKj. Therefore, when the selected clock is Pfi,
CLOCK SYNCHRONOUS SERIAL COMMUNI-
CATION
Bit Rate = Pfi/ {(n+1)×2}
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 59 will be described.
(The transmission side will be denoted by subscript j and the receiv-
ing side will be denoted by subscript k.)
On the clock receiving side, the TCS0 and TCS1 bits of the UARTk
Transmit/Receive control register 0 are ignored because an external
clock is selected.
Bit 0 of the UARTj Transmit/Receive mode register and UARTk
Transmit/Receive mode register must be set to “1” and bits 1 and 2
must be “0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj Transmit/Receive mode register of the clock send-
ing side is cleared to “0” to select the internal clock. Bit 3 of the
UARTk Transmit/Receive mode register of the clock receiving side is
set to “1” to select the external clock. Bits 4, 5 and 6 are ignored in
clock synchronous mode. Bit 7 must always be “0”.
Bit 2 of the clock-sending-side UARTj Transmit/Receive control reg-
____
ister 0 is cleared to “0” to select CTSj input. Bit 2 of the clock receiv-
____
ing side is set to “1” to select RTSk output.
Bit 4 of the UART Transmit/Receive control register 0 is used to de-
____ ____
termine whether to use CTS or RTS signal. Bit 4 must be “0” when
____ ____
____
____
CTS or RTS signal is used. Bit 4 must be “1” when CTS and RTS sig-
____ ____ ____
nals are not used. When CTS and RTS signals are not used, CTS/
____ ____ ____
RTS pin can be used as a normal port. The case using CTS and RTS
____ ____
The clock source is selected by bit 0 (TCS0) and bit 1 (TCS1) of the
clock-sending-side UARTj Transmit/Receive control register 0. As
shown in Figure 54, the selected clock is divided by (n+1), then by 2,
is passed through a transmission control circuit, and is output as
signals are explained below. However, when CTS and RTS signals
____
are not used, there are no condition of CTSj input, and there is no
_____
RTSk output.
TxDj
TxDk
UARTj transmit register
UARTk transmit register
UARTj transmit buffer register
UARTj receive buffer register
UARTk transmit buffer register
UARTk receive buffer register
RxDj
RxDk
UARTj receive register
UARTk receive register
UARTj Transmit/Receive mode register
UARTk Transmit/Receive mode register
×
×
×
×
×
×
0
0
0
0
1
0
1
0
0
1
CLKj
CTSj
CLKk
RTSk
UARTj Transmit/Receive control
register 0
UARTk Transmit/Receive control
register 0
MSB/
LSB
TX
MSB/
LSB
TX
×
×
0
TCS1 TCS0
1
EPTY
EPTY
UARTj Transmit/Receive control
register 1
UARTk Transmit/Receive control
register 1
SUM PER FER OER RI
RE
TI
TE
SUM PER FER OER RI
RE
TI
TE
Fig. 59 Clock synchronous serial communication
48
RENESAS [ RENESAS TECHNOLOGY CORP ]
