MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
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Once transmission has started, the TEi flag, TIi flag, and CTSi signal
____
Transmission
(if CTSi input is selected ) are ignored until data transmission is com-
pleted.
Transmission is started when bit 0 (TEi flag) of UARTi Transmit/Re-
____
ceive control register 1 is “1”, bit 1 (TIi flag) is “0”, and CTSi input is
____
Therefore, transmission does not stop until it completes event if the
TEi flag is cleared during transmission.
“L” if CTSi input is selected. As shown in Figures 65 and 66, data is
output from the TXDi pin with the stop bit or parity bit specified by bits
4 to 6 of UARTi Transmit/Receive mode register. The data is output
from the least significant bit.
The transmission start condition indicated by TEi flag, TIi flag, and
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CTSi is checked while the TENDi signal shown in Figure 65 is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIi flag is
cleared to “0” before the TENDi signal goes “H”.
The TIi flag indicates whether the transmit buffer is empty or not. It is
cleared to “0” when data is written in the transmit buffer, and is set to
“1” when the contents of the transmit buffer register is transferred to
the transmit register.
Bit 3 (TXEPTYi flag) of UARTi Transmit/Receive control register 0
changes to “1” at the next cycle just after the TENDi signal goes “H”
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission is completed.
When the TIi flag changes from “0” to “1”, the interrupt request bit of
the UARTi transmit interrupt control register is set to “1”.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmit start condi-
tion is satisfied.
(1/Pfi or 1/fEXT) × (n + 1) × 16
Transmission clock
TE
i
TI
i
Written in transmit buffer register
Transmit register ← Transmit
buffer register
CTS
i
T
T
T
ENDi
Stopped because TE
ST
i = “0”
Start bit
ST
Parity bit Stop bit
SP ST
X
X
Di
D0
D1
D2
D3
D4
D5
D6
D
7
P
D
0
D1
D2
D3
D4
D5
D6
D7
P
SP
D0 D1
EPTY
i
Fig. 65 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected
(1/Pfi or 1/fEXT) × (n + 1) × 16
Transmission clock
TEi
TI
i
Written in transmit buffer register
Start bit
Transmit register ← Transmit
buffer register
T
T
T
ENDi
Stopped because TE
i = “0”
Stop bit Stop bit
SP SP ST
X
X
Di
ST
D0
D1
D
2
D3
D4
D5
D6
D7
D8
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP SP ST D0 D1 D2
EPTY
i
Fig. 66 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected
54
RENESAS [ RENESAS TECHNOLOGY CORP ]
