MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
changes to “1” at the next cycle just after the TENDj signal goes “H”
Transmission
and changes to “0” when transmission starts. Therefore, this flag can
be used to determine whether data transmission has completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit in
the UARTj transmit interrupt control register is set to “1”.
Transmission is started when bit 0 (TEj flag) of UARTj Transmit/Re-
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ceive control register 1 is “1”, bit 1 (TIj flag) of one is “0”, and CTSj
input is “L”. As shown in Figure 60, data is output from TXDj pin each
time when transmission clock CLKj changes from “H” to “L”. The data
is output from the least significant bit.
In only UART0, data can be output to a maximum of 3 external re-
ceive devices. This is realized under the condition in which the inter-
nal clock is selected and the transmission clock is output from one of
The TIj flag indicates whether the transmit buffer register is empty or
not. It is cleared to “0” when data is written in the transmit buffer reg-
ister and set to “1” when the contents of the transmit buffer register is
transferred to the transmit register.
pins CLK0, CLKS0 (multiplexed with RXD0) and CLKS1 (multiplexed
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with CTS0/RTS0). Make sure that do not switch the selection of the
clock during transmission. Figure 61 shows an external connection
example.
When the transmit register becomes empty after the contents has
been transmitted, data is transferred automatically from the transmit
buffer register to the transmit register if the next transmission start
Plural output of transmit clock mode is set with bits 1 and 0 of the
particular function select register 1. Additionally, it is necessary to se-
condition is satisfied. If bit 2 of UARTj Transmit/Receive control reg-
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___
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lect the internal clock, disable CTS and RTS, receive and D-A output
with the UART0 Transmit/Receive mode register, UART0 Transmit/
Receive control registers 0 and 1, and A-D control register 1. Figure
62 shows the other registers bit configuration in plural output of trans-
mit clock mode and Figure 63 shows the particular function select
register 1 bit configuration .
ister 0 is “1”, CTSj input is ignored, and transmission start is con-
trolled only by the TEj flag and TIj flag. Once transmission has
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started, the TEj flag, TIj flag, and CTSj signals are ignored until data
transmission completes. Therefore, transmission is not interrupt
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when CTSj input is changed to “H” during transmission.
The transmission start condition indicated by TEj flag, TIj flag, and
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Table 6 shows the function of the particular function select register
1’s bits 1 and 0, which is the output pin of transmit clock select bits:
TC1 and TC0. According to this table, select the CLK0, CLKS0 or
CLKS1 pin corresponding to the contents of TC1 and TC0, and out-
put the transmit clock.
CTSj is checked while the TENDj signal (shown in Figure 60) is “H”.
Therefore, data can be transmitted continuously if the next transmis-
sion data is written in the transmit buffer register and TIj flag is
cleared to “0” before theTENDj signal goes “H”.
Bit 3 (TXEPTYj flag) of UARTj Transmit/Receive control register 0
1/Pfi × (n + 1) × 2
Transmission
clock
TE
TIj
j
Write in transmit buffer register
Transmit register ←Transmit buffer register
CTSj
1/Pfi × (n + 1) × 2
Stopped because TEj = “0”
CLKj
TENDj
TXDj
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
TXEPTYj
Fig. 60 Clock synchronous serial I/O timing
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RENESAS [ RENESAS TECHNOLOGY CORP ]
