MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
For the main data slice line, the count value of pulses in the window
is stored in clock run-in register 1 (address 00E616; refer to Figure
30). For the sub-data slice line, the count value of pulses in the window
is stored in clock run-in register 3 (address 020916; refer to Figure
29). When this count value is 4 to 6, it is determined as a clock run-in.
Accordingly, set the count value so that the window may start after
the first pulse of the clock run-in (refer to Figure 32).
7
0
0
Clock run-in register 1
(CR1 : address 00E616)
1
0 1
Clock run-in count value of
main-data slice line
The contents to be set in the window register are written at a falling
of the horizontal synchronizing signal. For this reason, even if an
instruction for setting is executed, the contents of the register cannot
be rewritten until a falling of the horizontal synchronizing signal.
For the main data slice line, reference clock is counted in the period
from a falling of the clock pulse set in bits 0 to 2 of the clock run-in
detect register 2 (address 00E916) to the next falling. The count value
is stored in bits 3 to 7 of the clock run-in detect register 1 (address
00E816) (When the count value exceeds “1F16,” “1F16” is held). For
the sub-data slice line, the count value is stored in bits 3 to 7 of the
clock run-in detect register 3 (address 020816). Read out these bits
after the occurence of a data slicer interrupt (refer to (11) Interrupt
Request Generating Circuit).
Fix these bits to “01012”
Fig. 30. Structure of clock run-in register 1
0
7
Clock run-in register 3
(CR3 : address 020916
)
Clock run-in count value of sub-data
slice line
Data latch completion flag for caption data in
sub-data slice line
0: Data is not latched yet
1: Data is latched
Figure 33 shows the structure of clock run-in detect registers 1 and
3.
Data slice line selection bit for interrupt
request
0: Main data slice line
1: Sub-data slice line
Interrupt mode selection bit
0: Interrupt occurs at end of data slice line
1: Interrupt occurs at completion of caption
data latch
Fig. 31. Structure of clock run-in register 3
Horizontal
synchronizing
signal
Start bit data +
16-bit data
Clock run-in
Composite
video signal
Window
✽When the count value
in the window is 4 to 6,
this is determined as a
clock run-in.
Time to be set in the
window register
Time to be set in
the start bit position
register
Fig. 32. Window setting
7
0
Clock run-in detect registers 1, 3
( CRD1 : address 00E816)
( CRD3 : address 020816)
Test bits : read-only
Number of reference clocks to
be counted in one clock run-in
pulse period
Fig. 33. Structure of clock run-in detect registers 1and 3
33
RENESAS [ RENESAS TECHNOLOGY CORP ]
