MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) Reference Voltage Generating Circuit and
Comparator
7
1
0
Caption position register
(CP : address 00E016)
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
➀Reference voltage generating circuit
0
0
This circuit generates a reference voltage (slice voltage) by using
the amplitude of the clock run-in pulse in line specified by the data
slice line specification circuit. Connect a capacitor between the
VHOLD pin and the VSS pin, and make the length of wiring as short
as possible so that a leakage current may not be generated.
➁Comparator
Specification main data slice line
Fix these bits to “1002”
Fig. 25. Structure of caption position register
The comparator compares the voltage of the composite video signal
with the voltage (reference voltage) generated in the reference
voltage generating circuit, and converts the composite video signal
into a digital value.
(7) Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit. For start bit detection, it is possible to select one
of the following two types by using bit 1 of the clock run-in register 2
(address 00E716).
7
0
Start bit position register
(SP : address 00E116)
➀After the lapse of the time corresponding to the set value of the
start bit position register (address 00E116), the first rising of the
composite video signal is detected as a start bit.
Start bit generating time
Time from a falling of the
horizontal synchronizing signal
to occurrence of a start bit = 4
✕ set value (“0016” to “7F16”) ✕
reference clock period
The time is set in bits 0 to 6 of the start bit position register (address
00E116) (refer to Figure 26). Set a value fit for the following
conditions.
Figure 26 shows the structure of the start bit position register.
DSC1 bit 7 control bit
0 : Generation of 16 pulses
1 : Generation of 16 pulses and
detection of clock run-in
Fig. 26. Structure of start bit position register
Time from the falling of the horizontal
synchronizing signal to the last rising
of the clock run-in
4 ✕ set value of the start bit position
register ✕ reference clock period
Time from the falling of the horizontal
synchronizing signal to occurrence of
the start bit
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RENESAS [ RENESAS TECHNOLOGY CORP ]
