M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
High-speed operation start
mode
Reset
STP instruction
WIT instruction
8 MHz oscillating
32 kHz oscillating
φ is stopped (“H”)
8 MHz oscillating
32 kHz oscillating
f(φ) = 4 MHz
8 MHz stopped
32 kHz stopped
φ is stopped (“H”)
Timer operating
Interrupt
Interrupt (See note 1)
External INT
External INT,
timer interrupt,
or SI/O interrupt
CM7 = 0
CM7 = 1
WIT instruction
Interrupt
STP instruction
8 MHz oscillating
32 kHz oscillating
φ is stopped (“H”)
Timer operating
(See note 3)
8 MHz oscillating
32 kHz oscillating
f(φ) = 16kHz
8 MHz stopped
32 kHz stopped
φ is stopped (“H”)
Interrupt (See note 2)
CM6 = 0
The program must
allow time for 8 MHz
oscillation to stabilize
CM6 = 1
STP instruction
WIT instruction
Interrupt
8 MHz stopped
32 kHz oscillating
φ is stopped (“H”)
Timer operating
(See note 3)
8 MHz stopped
32 kHz stopped
φ = stopped (“H”)
8 MHz stopped
32 kHz oscillating
f(φ) = 16 kHz
Interrupt (See note 2)
CPU mode register
(Address : 00FB16
)
CM6 : Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
CM7 : Internal system clock selection bit
0 : XIN-XOUT selected (high-speed mode)
1 : XCIN-XCOUT selected (low-speed mode)
The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. The φ indicates the internal clock.
Notes 1: When the STP state is ended, a delay of approximately 8 ms is automatically generated by timer 3 and timer 4.
2: The delay after the STP state ends is approximately 2s.
3: When the internal clock φ divided by 8 is used as the timer count source, the frequency of the count source is 2 kHz.
Fig.8.13.6 State Transitions of System Clock
Rev.1.00 2003.11.25 page 87 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
