M37161M8/MA/MF-XXXSP/FP,M37161EFSP/FP
8.12 RESET CIRCUIT
When the oscillation of a quartz-crystal oscillator or a ceramic reso-
nator is stable and the power source voltage is 5 V ± 10 %, hold the
RESET pin at LOW for 2 µs or more, then return to HIGH. Then, as
shown in Figure 8.12.2, reset is released and the program starts from
the address formed by using the content of address FFFF16 as the
high-order address and the content of the address FFFE16 as the
low-order address. The internal states of the microcomputer at reset
are shown in Figures 8.2.2 to 8.2.5.
Power on
4.5 V
0.9 V
Power source voltage 0 V
Reset input voltage 0 V
An example of the reset circuit is shown in Figure 8.12.1.
The reset input voltage must be kept 0.9 V or less until the power
source voltage surpasses 4.5 V.
Vcc
1
5
RESET
M51953AL
4
0.1 µF
3
Vss
Microcomputer
Fig.8.12.1 Example of Reset Circuit
X
IN
φ
RESET
Internal RESET
SYNC
AD
AD
H
L
,
Address
Data
01, S-1
01, S-2
FFFE FFFF
?
?
01, S
Reset address from the vector table
AD
L
ADH
?
?
?
?
?
Notes 1 : f(XIN) and f(φ) are in the relation : f(XIN) = 2·f (φ).
2 : A question mark (?) indicates an undefined state that
depends on the previous state.
32768 count of XIN
clock cycle (See note 3)
3 : Immediately after a reset, timer 3 and timer 4 are
connected by hardware. At this time, “FF16” is set
in timer 3 and “0716” is set to timer 4. Timer 3 counts down
with f(XIN)/16, and reset state is released by the timer 4
overflow signal.
Fig.8.12.2 Reset Sequence
Rev.1.00 2003.11.25 page 83 of 128
RENESAS [ RENESAS TECHNOLOGY CORP ]
