DMAC
9.3 Functional Description of the DMAC
9
(5) Transfer count value
The transfer count value is decremented one at a time, irrespective of the size of transfer unit (8 or 16 bits).
(6) Transfer byte positions
When the transfer unit is 8 bits, the LSB of the address register is effective for both source and destination.
(Therefore, in addition to data transfers between even addresses or between odd addresses, data may be
transferred from even address to odd address or vice versa.) When the transfer unit is 16 bits, the LSB of the
address register (= bit 15) is ignored, and data are always transferred in two bytes aligned to the 16-bit bus.
The diagram below shows the valid byte positions in DMA transfer.
<When transfer size = 8 bits>
<When transfer size = 16 bits>
+0 +1
+0
+1
b0
b7 b8
b15
b0
b7 b8
b15
Source
16 bits
8 bits
8 bits
Destination
16 bits
8 bits
8 bits
Figure 9.3.3 Transfer Byte Positions
(7) Ring buffer mode
When ring buffer mode is selected, transfer begins from the transfer start address and after performing
transfers 32 times, control returns to the transfer start address, from which transfer operation is repeated. In
this case, however, the five low-order bits of the ring buffer start address must always be B’00000 (if transfer
size = 16 bits, the six low-order bits must be B’000000).
The following describes how addresses are incremented in ring buffer mode.
[1] When the transfer size is 8 bits
The 27 high-order bits of the transfer start address are fixed, and the five low-order bits are incremented
by one at a time. When as transfer proceeds the five low-order bits reach B’11111, they are recycled to
B’00000 by the next increment operation, thus returning to the start address again.
[2] When the transfer size is 16 bits
The 26 high-order bits of the transfer start address are fixed, and the six low-order bits are incremented
by two at a time. When as transfer proceeds the six low-order bits reach B’111110, they are recycled to
B’000000 by the next increment operation, thus returning to the start address again.
If the source address has been set to be incremented, it is the source address that recycles to the start
address; if the destination address has been set to be incremented, it is the destination address that recycles
to the start address. If both source and destination addresses have been set to be incremented, both ad-
dresses recycle to the start address. However, the start address on either side must have their five low-order
bits initially set to B’00000 (if transfer size = 16 bits, the six low-order bits must be B’000000).
During ring buffer mode, the transfer count register is ignored. Once DMA operation starts, the counter operates
in free-run mode, and the transfer continues until the transfer enable bit is cleared to "0" (to disable transfer).
32180 Group User’s Manual (Rev.1.0)
9-36
RENESAS [ RENESAS TECHNOLOGY CORP ]
