DMAC
9.2 DMAC Related Registers
9
Example for clearing interrupt request status
Interrupt request status
b4
0
5
0
6
0
b7
0
Initial state
Interrupt request
Event occurs on bit 6
0
1
0
0
1
1
0
0
Event occurs on bit 4
Write to the interrupt request status
b4
1
5
1
6
0
b7
1
1
0
0
0
Only bit 6 cleared
Bit 4 data retained
Program example
• To clear the Interrupt Request Status Register 0 (ISTREG) interrupt request status 1, ISTAT1 (0x02 bit)
ISTREG = 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
To clear an interrupt request status, always be sure to write "1" to all other interrupt request status bits. At this time,
avoid using a logic operation like the one shown below. Because it requires three step-ISTREG read, logic operation
and write, if another interrupt request occurs between the read and write, status may be inadvertently cleared.
ISTREG &= 0xfd;
/* Clear ISTAT1 (0x02 bit) only */
Interrupt request status
b4
0
5
6
1
b7
0
Event occurs on bit 6
0
Read
0
0
0
1
0
0
1
0
0
0
1
0
0
0
Clear bit 6 (AND'ing with 1101)
0
Event occurs on bit 4
0
Write
Only bit 6 cleared
Bit 4 also cleared
Figure 9.2.3 Example for Clearing Interrupt Request Status
32180 Group User’s Manual (Rev.1.0)
9-23
RENESAS [ RENESAS TECHNOLOGY CORP ]
