M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode (with a wait state)
Read Timing
BCLK
18ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
18ns.max(1)
t
h(RD-CS)
0ns.min
tcyc
t
h(BCLK-AD)
t
d(BCLK-AD)
18ns.max(1)
0ns.min
ADi
BHE
t
d(BCLK-RD)
18ns.max
t
h(RD-AD)
0ns.min
RD
DB
t
h(BCLK-RD)
-3ns.min
t
ac2(RD-DB)(2)
ac2(AD-DB)(2)
t
Hi-Z
tsu(DB-BCLK)
t
h(RD-DB)
0ns.min
30ns.min(1)
NOTES:
1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is guaranteed
for td(BCLK-AD)+tsu(DB-BCLK)
.
2. Varies with operation frequency.
t
t
ac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states)
ac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states)
Write Timing
BCLK
18ns.max
td(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
18ns.max
CSi
t
t
h(WR-CS)(1)
h(WR-AD)(1)
tcyc
t
d(BCLK-AD)
18ns.max
t
h(BCLK-AD)
0ns.min
ADi
BHE
t
d(BCLK-WR)
18ns.max
t
w(WR)(1)
WR,WRL,
WRH
t
h(BCLK-WR)
0ns.min
h(WR-DB)(1)
t
d(DB-WR)(1)
t
DBi
NOTES:
1. Varies with operation frequency.
d(DB-WR)=(tcyc x n-20)ns.min
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage:
t
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait
states)
V
IH=1.5V, VIL=0.5V
• Output high and low voltage:
OH=1.5V, VOL=1.5V
t
t
t
t
h(WR-DB)=(tcyc/2-10)ns.min
h(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min
w(WR)=(tcyc/2 x n-15)ns.min
V
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait
states)
Figure 5.11 VCC=3.3V Timing Diagram (2)
Page 74
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
