M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(With 2 wait states, when accessing the DRAM area)
Write Timing
BCLK
tcyc
td(BCLK-RAD)
18ns.max
td(BCLK-CAD)
18ns.max
th(BCLK-RAD)
0ns.min
th(BCLK-CAD)
0ns.min
MAi
Column address
Row address
th(RAS-RAD)(1)
tRP(1)
RAS
td(BCLK-RAS)
18ns.max
th(BCLK-RAS)
td(BCLK-CAS)
18ns.max
0ns.min
CASL
CASH
th(BCLK-CAS)
0ns.min
td(BCLK-DW)
18ns.max
DW
DB
th(BCLK-DW)
-3ns.min
tsu(DB-CAS)(1)
Hi-Z
th(BCLK-DB)
-7ns.min
Measurement Conditions:
• VCC=3.0 to 3.6V
NOTES:
1. Varies with operation frequency.
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
• Input high and low voltage:
VIH=1.5V, VIL=0.5V
• Output high and low voltage:
VOH=1.5V, VOL=1.5V
tsu(DB-CAS)=(tcyc-20)ns.min
Figure 5.14 VCC=3.3V Timing Diagram (5)
Page 77
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
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