M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
Read Timing
BCLK
t
d(BCLK-ALE)
18ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
tcyc
t
d(BCLK-CS)
18ns.max
t
h(RD-CS)(1)
h(ALE-AD)(1)
t
d(AD-ALE)(1)
t
ADi
/DBi
Address
Address
Data input
t
dz(RD-AD)
t
h(RD-DB)
0ns.min
8ns.max
t
su(DB-BCLK)
30ns.min
t
h(BCLK-AD)
t
d(BCLK-AD)
18ns.max
t
ac3(RD-DB)(1)
0ns.min
ADi
BHE
h(RD-AD)(1)
t
ac3(AD-DB)(1)
t
d(BCLK-RD)
t
t
h(BCLK-RD)
-3ns.min
18ns.max
RD
NOTES:
1. Varies with operation frequency.
t
t
t
t
d(AD-ALE)=(tcyc/2-20)ns.min
h(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
ac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
ac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write Timing
BCLK
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
18ns.max
ALE
CSi
t
h(BCLK-CS)
tcyc
h(WR-CS)(1)
t
d(BCLK-CS)
18ns.max
0ns.min
t
d(AD-ALE)(1)
t
h(ALE-AD)(1)
Address
t
ADi
/DBi
Address
Data output
d(DB-WR)(1)
h(WR-DB)(1)
t
t
t
h(BCLK-AD)
0ns.min
t
d(BCLK-AD)
18ns.max
ADi
BHE
t
h(WR-AD)()
t
h(BCLK-WR)
0ns.min
t
d(BCLK-WR)
18ns.max
WR,WRL,
WRH
NOTES:
Measurement Conditions:
• VCC=3.0 to 3.6V
1. Varies with operation frequency.
t
t
t
t
d(AD-ALE)=(tcyc/2-20)ns.min
• Input high and low voltage:
h(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
d(DB-WR)=(tcyc/2 x m-25)ns.min
V
IH=1.5V, VIL=0.5V
• Output high and low voltage:
OH=1.5V, VOL=1.5V
V
(m=3 with 2 wait states and m=5 with 3 wait states)
Figure 5.12 VCC=3.3V Timing Diagram (3)
Page 75
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
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