M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
o
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)
Table 5.43 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting a Space with the
Multiplexed Bus)
Standard
Measurement
Condition
Symbol
Parameter
Unit
Min
Max
18
td(BCLK-AD)
th(BCLK-AD)
Address Output Delay Time
ns
ns
Address Output Hold Time (BCLK standard)
0
th(RD-AD)
Address Output Hold Time (RD standard)
Address Output Hold Time (WR standard)
Chip-select Signal Output Delay Time
(Note 1)
(Note 1)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
18
Chip-select Signal Output Hold Time (BCLK standard)
Chip-select Signal Output Hold Time (RD standard)
Chip-select Signal Output Hold Time (WR standard)
RD Signal Output Delay Time
0
(Note 1)
th(WR-CS)
See Figure 5.1 (Note 1)
td(BCLK-RD)
th(BCLK-AD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
18
18
RD Signal Output Hold Time
-3
WR Signal Output Delay Time
WR Signal Output Hold Time
0
Data Output Delay Time (WR standard)
Data Output Hold Time (WR standard)
ALE Signal Output Delay Time (BCLK standard)
ALE Signal Output Hold Time (BCLK standard)
ALE Signal Output Delay Time (address standard)
ALE Signal Output Hold Time (address standard)
Address Output High-Impedance Time
(Note 1)
(Note 1)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
tdz(RD-AD)
NOTES:
18
8
-2
(Note 1)
(Note 1)
1. Values can be obtained from the following equations, according to BCLK frequency.
10 9
th(RD – AD)
th(WR – AD)
th(RD – CS)
th(WR – CS)
=
– 10 [ns]
– 10 [ns]
f
f
f
f
(BCLK) X 2
10 9
=
(BCLK) X 2
10 9
(BCLK) X 2
10 9
=
–10
[ns]
=
– 10 [ns]
(BCLK) X 2
109X m
t
t
t
d(DB – WR)
h(WR – DB)
d(AD – ALE)
=
=
– 25 [ns] (m=3 with 2 wait states and m=5 with 3 wait states)
– 10 [ns]
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9
=
– 20 [ns]
– 10 [ns]
f(BCLK) X 2
10 9
th(ALE – AD) =
f(BCLK) X 2
Page 71
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
