M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
o
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)
Table 5.44 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Area)
Standard
Measurement
Condition
Symbol
Parameter
Unit
Min
Max
18
td(BCLK-RAD) Row Address Output Delay Time
ns
ns
th(BCLK-RAD) Row Address Output Hold Time (BCLK standard)
0
td(BCLK-CAD) Column Address Output Delay Time
18
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(BCLK-CAD) Column Address Output Hold Time (BCLK standard)
th(RAS-RAD) Row Address Output Hold Time after RAS Output
td(BCLK-RAS) RAS Output Delay Time (BCLK standard)
th(BCLK-RAS) RAS Output Hold Time (BCLK standard)
0
(Note 1)
0
See Figure 5.1
tRP
RAS High ("H") Hold Time
(Note 1)
td(BCLK-CAS) CAS Output Delay Time (BCLK standard)
th(BCLK-CAS) CAS Output Hold Time (BCLK standard)
td(BCLK-DW) DW Output Delay Time (BCLK standard)
th(BCLK-DW) DW Output Hold Time (BCLK standard)
tsu(DB-CAS) CAS Output Setup Time after DB output
th(BCLK-DB) DB Signal Output Hold Time (BCLK standard)
tsu(CAS-RAS) CAS Output Setup Time before RAS Output (refresh)
NOTES:
18
18
0
-3
(Note 1)
-7
(Note 1)
1. Values can be obtained from the following equations, according to the BCLK frequency.
10 9
t
h(RAS – RAD) =
– 13 [ns]
f
(BCLK) X 2
109 X 3
tRP
=
– 20 [ns]
f
(BCLK) X 2
10 9
tsu(DB – CAS) =
– 20
[ns]
f
(BCLK)
109
t
su(CAS – RAS)
=
– 13 [ns]
f
(BCLK) X 2
Page 72
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
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