M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode
(With 2 wait states, when accessing the DRAM area)
Read Timing
BCLK
tcyc
td(BCLK-CAD)
th(BCLK-CAD)
0ns.min
th(BCLK-RAD)
18ns.max(1)
td(BCLK-RAD)
18ns.max(1)
0ns.min
Row address
th(RAS-RAD)(1)
MAi
Column address
tRP(2)
RAS
th(BCLK-RAS)
td(BCLK-RAS)
18ns.max(1)
td(BCLK-CAS)
18ns.max(1)
0ns.min
CASL
CASH
th(BCLK-CAS)
0ns.min
DW
DB
tac4(CAS-DB)(2)
tac4(CAD-DB)(2)
tac4(RAS-DB)(2)
Hi-Z
tsu(DB-BCLK)
30ns.min(1)
th(CAS-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently. A maximum of 35ns is
guaranteed for the followings:
td(BCLK-RAS) + tsu(DB-BCLK)
td(BCLK-CAS) + tsu(DB-BCLK)
td(BCLK-CAD) + tsu(DB-BCLK)
2. It varies with the operation frequency.
tac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
tac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
tac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
th(RAS-RAD)=(tcyc/2-13)ns.min
tRP=(tcyc/2 x 3-20)ns.min
Measurement Conditions:
• VCC=3.0 to 3.6V
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.13 VCC=3.3V Timing Diagram (4)
Page 76
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
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