M32C/83 Group (M32C/83, M32C/83T)
VCC=3.3V
Switching Characteristics
o
(VCC = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)
Table 5.42 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory)
Standard
Measurement
Symbol
Parameter
Address Output Delay Time
Unit
Condition
Min
Max
18
td(BCLK-AD)
ns
ns
th(BCLK-AD)
Address Output Hold Time (BCLK standard)
0
0
th(RD-AD)
Address Output Hold Time (RD standard)
Address Output Hold Time (WR standard)
Chip-select Signal Output Delay Time
Chip-select Signal Output Hold Time (BCLK standard)
Chip-select Signal Output Hold Time (RD standard)
Chip-select Signal Output Hold Time (WR standard)
ALE Signal Output Delay Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(WR-AD)
(Note 1)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
18
0
0
See Figure 5.1
th(WR-CS)
(Note 1)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
18
18
18
ALE Signal Output Hold Time
-2
-3
RD Signal Output Delay Time
RD Signal Output Hold Time
WR Signal Output Delay Time
th(BCLK-WR) WR Signal Output Hold Time
0
td(DB-WR)
th(WR-DB)
tw(WR)
Data Output Delay Time (WR standard)
(Note 1)
(Note 1)
(Note 1)
Data Output Hold Time (WR standard)
WR Output Width
NOTES:
1. Values can be obtained from the following equations, according to BCLK frequency.
10 9 X n
td(DB – WR) =
th(WR – DB) =
th(WR – AD) =
th(WR – CS) =
– 20
[ns] (n=1 with 1 wait state, n=2 with 2 wait states
and n=3 with 3 wait states)
f(BCLK)
10 9
– 10
– 10
– 10
[ns]
[ns]
[ns]
f(BCLK) X 2
10 9
f(BCLK) X 2
10 9
f(BCLK) X 2
109 X n
f(BCLK) X 2
tw( WR) =
– 15 [ns] (n=1 with 1 wait state, n=3 with 2 wait states
and n=5 with 3 wait states)
Page 70
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
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