M32C/83 Group (M32C/83, M32C/83T)
Vcc=3.3V
Memory Expansion Mode and Microprocessor Mode (with no wait state)
Read Timing
BCLK
t
d(BCLK-ALE)
18ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
18ns.max(1)
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
t
h(BCLK-AD)
18ns.max(1)
0ns.min
ADi
BHE
t
h(RD-AD)
0ns.min
t
d(BCLK-RD)
18ns.max
RD
DB
t
ac2(RD-DB)(2)
t
h(BCLK-RD)
-3ns.min
t
ac2(AD-DB)(2)
Hi-Z
t
su(DB-BCLK)
30ns.min(1)
t
h(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK)
2. Varies with operation frequency:
.
t
t
ac2(RD-DB)=(tcyc/2-35)ns.max
ac2(AD-DB)=(tcyc-35)ns.max
Write Timing
BCLK
t
d(BCLK-ALE)
18ns.max
th(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
0ns.min
t
d(BCLK-CS)
18ns.max
h(WR-CS)(1)
tcyc
t
t
d(BCLK-AD)
18ns.max
t
h(BCLK-AD)
0ns.min
ADi
BHE
t
h(WR-AD)(1)
t
d(BCLK-WR)
18ns.max
t
w(WR)(1)
WR,WRL,
WRH
t
h(BCLK-WR)
0ns.min
d(DB-WR)(1)
t
h(WR-DB)(1)
t
DBi
Measurement Conditions:
NOTES:
1. Varies with operation frequency.
• VCC=3.0 to 3.6V
t
t
t
t
t
d(DB-WR)=(tcyc-20)ns.min
h(WR-DB)=(tcyc/2-10)ns.min
h(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min
w(WR)=(tcyc/2-15)ns.min
• Input high and low voltage: VIH=1.5V, VIL=0.5V
• Output high and low voltage: VOH=1.5V, VOL=1.5V
Figure 5.10 VCC=3.3V Timing Diagram (1)
Page 73
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
