M32C/83 Group (M32C/83, M32C/83T)
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
Vcc=5V
Write Timing
BCLK
tcyc
t
d(BCLK-RAD)
t
d(BCLK-CAD)
18ns.max
t
h(BCLK-CAD)
t
h(BCLK-RAD)
-3ns.min
18ns.max
-3ns.min
MAi
Column address
Row address
RP(1)
t
h(RAS-RAD)(1)
t
RAS
t
h(BCLK-RAS)
-3ns.min
t
d(BCLK-RAS)
18ns.max
td(BCLK-CAS)
18ns.max
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
td(BCLK-DW)
18ns.max
DW
DB
t
h(BCLK-DW)
-5ns.min
t
su(DB-CAS)(1)
Hi-Z
t
h(BCLK-DB)
-7ns.min
NOTES:
1. Varies with operation frequency:
t
t
t
h(RAS-RAD)=(tcyc/2-13)ns.min
RP=(tcyc/2 x 3-20)ns.min
su(DB-CAS)=(tcyc-20)ns.min
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.6 VCC=5V Timing Diagram (5)
Page 60
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
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