M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
t
c(TA)
tw(TAH)
TAiIN input
t
w(TAL)
t
c(UP)
t
w(UPH)
TAiOUT input
TAiOUT input
t
w(UPL)
(Counter increment/
decrement input)
In event counter mode
TAiIN input
(When counting on the falling edge)
t
h(TIN–UP)
tsu(UP–TIN)
TAiIN input
(When counting on the rising edge)
t
c(TB)
tw(TBH)
TBiIN input
t
w(TBL)
tc(AD)
tw(ADL)
ADTRG input
t
c(CK)
t
w(CKH)
CLKi
t
w(CKL)
t
h(C–Q)
TxDi
RxDi
t
d(C–Q)
tsu(D–C)
t
h(C–D)
tw(INL)
INTi input
NMI input
t
w(INH)
2 clock cycles + 300ns 2 clock cycles + 300ns
ore more ("L" width) or more
Figure 5.8 VCC=5V Timing Diagram (7)
Page 62
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
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