M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode
(with a wait state, when accessing an external memory and using the multiplexed bus)
Read Timing
BCLK
18ns.max
th(BCLK-ALE)
-2ns.min
td(BCLK-ALE)
ALE
CSi
th(BCLK-CS)
-3ns.min
tcyc
td(BCLK-CS)
18ns.max
th(RD-CS)(1)
td(AD-ALE)(1)
th(ALE-AD)(1)
ADi
/DBi
Address
Data input
Address
tdz(RD-AD)
8ns.max
th(RD-DB)
0ns.min
tsu(DB-BCLK)
26ns.min
td(BCLK-AD)
18ns.max
th(BCLK-AD)
-3ns.min
tac3(RD-DB)(1)
ADi
BHE
tac3(AD-DB)(1)
th(RD-AD)(1)
td(BCLK-RD)
18ns.max
th(BCLK-RD)
-5ns.min
RD
NOTES:
1. Varies with operation frequency:
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(RD-AD)=(tcyc/2-10)ns.min, th(RD-CS)=(tcyc/2-10)ns.min
tac3(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 2 wait states and m=5 with 3 wait states)
tac3(AD-DB)=(tcyc/2 x n-35)ns.max (n=5 with 2 wait states and n=7 with 3 wait states)
Write Timing (written in 2 cycles with no wait state)
BCLK
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
ALE
CSi
th(BCLK-CS)
-3ns.min
tcyc
td(BCLK-CS)
18ns.max
th(WR-CS)(2)
th(ALE-AD)(1)
td(AD-ALE)(2)
ADi
/DBi
Data output
td(DB-WR)(2)
Address
Address
th(WR-DB)(2)
th(WR-AD)(2)
th(BCLK-AD)
-3ns.min
td(BCLK-AD)
18ns.max
ADi
BHE
th(BCLK-WR)
-3ns.min
td(BCLK-WR)
18ns.max
WR,WRL,
WRH
NOTES:
Measurement Conditions:
2. Varies with operation frequency:
td(AD-ALE)=(tcyc/2-20)ns.min
th(ALE-AD)=(tcyc/2-10)ns.min, th(WR-AD)=(tcyc/2-10)ns.min
th(WR-CS)=(tcyc/2-10)ns.min, th(WR-DB)=(tcyc/2-10)ns.min
td(DB-WR)=(tcyc/2 x m-25)ns.min
• VCC=4.2 to 5.5V
• Input high and low voltage:
VIH=2.5V, VIL=0.8V
• Output high and low voltage:
VOH=2.0V, VOL=0.8V
Figure 5.4 VCC=5V Timing Diagram (3)
Page 58
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
