M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode
(When accessing the DRAM area)
Read Timing
BCLK
tcyc
t
d(BCLK-CAD)
18ns.max(1)
t
d(BCLK-RAD)
t
h(BCLK-CAD)
t
h(BCLK-RAD)
18ns.max
-3ns.min
-3ns.min
Row address
h(RAS-RAD)(2)
MAi
Column address
RP(2)
t
t
RAS
t
h(BCLK-RAS)
-3ns.min
t
d(BCLK-RAS)
t
d(BCLK-CAS)
18ns.max(1)
18ns.max(1)
CASL
CASH
t
h(BCLK-CAS)
-3ns.min
DW
DB
t
ac4(CAS-DB)(2)
ac4(CAD-DB)(2)
ac4(RAS-DB)(2)
t
t
Hi-Z
t
su(DB-BCLK)
26ns.min(1)
t
h(CAS-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for the following combinations.
t
t
t
d(BCLK-RAS) + tsu(DB-BCLK)
d(BCLK-CAS) + tsu(DB-BCLK)
d(BCLK-CAD) + tsu(DB-BCLK)
2. Varies with operation frequency:
t
t
t
t
t
ac4(RAS-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state and m=5 with 2 wait states)
ac4(CAS-DB)=(tcyc/2 x n-35)ns.max (n=1 with 1 wait state and n=3 with 2 wait states)
ac4(CAD-DB)=(tcyc x l-35)ns.max (l=1 with 1 wait state and l=2 with 2 wait states)
h(RAS-RAD)=(tcyc/2-13)ns.min
RP=(tcyc/2 x 3-20)ns.min
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
Figure 5.5 VCC=5V Timing Diagram (4)
Page 59
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
