M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode
(Valid only with a wait state)
BCLK
RD
(Separate bus)
WR, WRL, WRH
(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH
(Multiplexed bus)
RDY input
t
h(BCLK–RDY)
t
su(RDY–BCLK)
(Valid with a wait state or with no wait state)
BCLK
t
su(HOLD–BCLK)
t
h(BCLK–HOLD)
HOLD input
HLDA output
t
d(BCLK–HLDA)
t
d(BCLK–HLDA)
P0, P1, P2,
P3, P4,
Hi–Z
P50 to P52
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=4.0V, VIL=1.0V
• Output high and low voltage: VOH=2.5V, VOL=2.5V
Figure 5.9 VCC=5V Timing Diagram (8)
Page 63
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
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