M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode (with a wait state)
Read Timing
BCLK
18ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max(1)
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
18ns.max(1)
t
h(BCLK-AD)
-3ns.min
ADi
BHE
t
d(BCLK-RD)
t
h(RD-AD)
0ns.min
18ns.max
RD
t
h(BCLK-RD)
-5ns.min
t
ac2(RD-DB)(2)
t
ac2(AD-DB)(2)
DB
Hi-Z
t
su(DB-BCLK)
26ns.min(1)
t
h(RD-DB)
0ns.min
Notes :
1. Value guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK)
2. Varies with operation frequency:
.
t
t
ac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3 with 1 wait state, m=5 with 2 wait states and m=7 with 3 wait states.)
ac2(AD-DB)=(tcyc x n-35)ns.max (n=2 with 1 wait state, n=3 with 2 wait states and n=4 with 3 wait states.)
Write Timing (written in 2 cycles with no wait state)
BCLK
18ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
t
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max
CSi
tcyc
t
h(WR-CS)(3)
h(BCLK-AD)
-3ns.min
t
d(BCLK-AD)
18ns.max
ADi
BHE
h(WR-AD)(3)
t
w(WR)(3)
t
t
d(BCLK-WR)
18ns.max
WR,WRL,
WRH
t
h(BCLK-WR)
-3ns.min
t
d(DB-WR)(3)
t
h(WR-DB)(3)
DBi
NOTES:
Measurement conditions
3. Varies with operation frequency:
d(DB-WR)=(tcyc x n-20)ns.min
(n=1 with 1 wait state, n=2 with 2 wait states and n=3 with 3 wait states)
• VCC=4.2 to 5.5V
• Input high and low voltage:
t
V
IH=2.5V, VIL=0.8V
• Output high and low voltage:
OH=2.0V, VOL=0.8V
t
t
t
t
h(WR-DB)=(tcyc/2-10)ns.min
h(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min
w(WR)=(tcyc/2 x n-15)ns.min
V
(n=1 with 1 wait state, n=3 with 2 wait states and n=5 with 3 wait states)
Figure 5.3 VCC=5V Timing Diagram (2)
Page 57
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
