M32C/83 Group (M32C/83, M32C/83T)
Vcc=5V
Memory Expansion Mode and Microprocessor Mode (with no wait state)
Read Timing
BCLK
t
d(BCLK-ALE)
18ns.max
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max(1)
t
h(RD-CS)
0ns.min
tcyc
t
d(BCLK-AD)
18ns.max(1)
t
h(BCLK-AD)
-3ns.min
ADi
BHE
t
d(BCLK-RD)
18ns.max
t
h(RD-AD)
0ns.min
RD
DB
t
h(BCLK-RD)
-5ns.min
t
ac1(RD-DB)(2)
t
ac1(AD-DB)(2)
Hi-Z
t
su(DB-BCLK)
26ns.min(1)
t
h(RD-DB)
0ns.min
NOTES:
1. Values guaranteed only when the microcomputer is used independently.
A maximum of 35ns is guaranteed for td(BCLK-AD)+tsu(DB-BCLK)
2. Varies with operation frequency:
.
t
t
ac1(RD-DB)=(tcyc/2-35)ns.max
ac1(AD-DB)=(tcyc-35)ns.max
Write Timing (written in 2 cycles with no wait state)
BCLK
18ns.max
t
d(BCLK-ALE)
t
h(BCLK-ALE)
-2ns.min
ALE
CSi
t
h(BCLK-CS)
-3ns.min
t
d(BCLK-CS)
18ns.max
tcyc
t
h(WR-CS)(3)
t
d(BCLK-AD)
t
h(BCLK-AD)
-3ns.min
18ns.max
ADi
BHE
t
h(WR-AD)(3)
t
d(BCLK-WR)
18ns.max
t
w(WR)(3)
WR,WRL,
WRH
t
h(BCLK-WR)
-3ns.min
h(WR-DB)(3)
t
d(DB-WR)(3)
t
DBi
NOTES:
3. Varies with operation frequency:
Measurement Conditions:
• VCC=4.2 to 5.5V
• Input high and low voltage: VIH=2.5V, VIL=0.8V
• Output high and low voltage: VOH=2.0V, VOL=0.8V
t
t
t
t
t
d(DB-WR)=(tcyc-20)ns.min
h(WR-DB)=(tcyc/2-10)ns.min
h(WR-AD)=(tcyc/2-10)ns.min
h(WR-CS)=(tcyc/2-10)ns.min
w(WR)=(tcyc/2-15)ns.min
Figure 5.2 VCC=5V Timing Diagram (1)
Page 56
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
