M32C/83 Group (M32C/83, M32C/83T)
VCC=5V
Switching Characteristics
o
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)
Table 5.23 Memory Expansion Mode and Microprocessor Mode
(With a Wait State, Accessing an External Memory and Selecting the DRAM Space)
Standard
Measurement
Condition
Symbol
Parameter
Unit
Min
Max
18
td(BCLK-RAD) Row Address Output Delay Time
ns
ns
th(BCLK-RAD) Row Address Output Hold Time (BCLK standard)
-3
td(BCLK-CAD) Column Address Output Delay Time
18
18
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
th(BCLK-CAD) Column Address Output Hold Time (BCLK standard)
th(RAS-RAD) Row Address Output Hold Time after RAS Output
td(BCLK-RAS) RAS Output Delay Time (BCLK standard)
th(BCLK-RAS) RAS Output Hold Time (BCLK standard)
-3
(Note 1)
See Figure 5.1
-3
tRP
RAS High ("H") Hold Time
(Note 1)
td(BCLK-CAS) CAS Output Delay Time (BCLK standard)
th(BCLK-CAS) CAS Output Hold Time (BCLK standard)
td(BCLK-DW) DW Output Delay Time (BCLK standard)
th(BCLK-DW) DW Output Hold Time (BCLK standard)
tsu(DB-CAS) CAS Output Setup Time after DB Output
th(BCLK-DB) DB Signal Output Hold Time (BCLK standard)
tsu(CAS-RAS) CAS Output Setup Time before RAS Output (refresh)
NOTES:
18
18
-3
-5
(Note 1)
-7
(Note 1)
1. Values can be obtained from the following equation, according to BCLK frequency.
10 9
[ns]
t
h(RAS – RAD) =
– 13
– 20
f
(BCLK) X 2
10 9X 3
t
RP
=
[ns]
[ns]
f
(BCLK) X 2
10 9
tsu(DB – CAS) =
– 20
f
(BCLK)
109
t
su(CAS – RAS)
=
[ns]
– 13
f
(BCLK) X 2
Page 54
Rev. 1.41 Jan.31, 2006
REJ03B0013-0141
of 91
RENESAS [ RENESAS TECHNOLOGY CORP ]
