欢迎访问ic37.com |
会员登录 免费注册
发布采购

M30833FJGP 参数 Datasheet PDF下载

M30833FJGP图片预览
型号: M30833FJGP
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片16位/ 32位微机的CMOS [SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER]
分类和应用: 外围集成电路计算机时钟
文件页数/大小: 94 页 / 841 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号M30833FJGP的Datasheet PDF文件第49页浏览型号M30833FJGP的Datasheet PDF文件第50页浏览型号M30833FJGP的Datasheet PDF文件第51页浏览型号M30833FJGP的Datasheet PDF文件第52页浏览型号M30833FJGP的Datasheet PDF文件第54页浏览型号M30833FJGP的Datasheet PDF文件第55页浏览型号M30833FJGP的Datasheet PDF文件第56页浏览型号M30833FJGP的Datasheet PDF文件第57页  
M32C/83 Group (M32C/83, M32C/83T)  
VCC=5V  
Switching Characteristics  
o
(VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85 C unless otherwise specified)  
Table 5.22 Memory Expansion Mode and Microprocessor Mode  
(With a Wait State, Accessing an External Memory and Selecting a Space with the  
Multiplexed Bus)  
Standard  
Measurement  
Condition  
Symbol  
Parameter  
Address Output Delay Time  
Unit  
Min  
Max  
18  
td(BCLK-AD)  
th(BCLK-AD)  
ns  
ns  
Address Output Hold Time (BCLK standard)  
-3  
th(RD-AD)  
Address Output Hold Time (RD standard)  
Address Output Hold Time (WR standard)  
Chip-select Signal Output Delay Time  
(Note 1)  
(Note 1)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
th(WR-AD)  
td(BCLK-CS)  
th(BCLK-CS)  
th(RD-CS)  
18  
Chip-select Signal Output Hold Time (BCLK standard)  
Chip-select Signal Output Hold Time (RD standard)  
Chip-select Signal Output Hold Time (WR standard)  
RD Signal Output Delay Time  
-3  
(Note 1)  
(Note 1)  
th(WR-CS)  
See Figure 5.1  
td(BCLK-RD)  
th(BCLK-AD)  
td(BCLK-WR)  
th(BCLK-WR)  
td(DB-WR)  
18  
18  
RD Signal Output Hold Time  
-5  
WR Signal Output Delay Time  
WR Signal Output Hold Time  
-3  
Data Output Delay Time (WR standard)  
Data Output Hold Time (WR standard)  
ALE Signal Output Delay Time (BCLK standard)  
ALE Signal Output Hold Time (BCLK standard)  
ALE Signal Output Delay Time (address standard)  
ALE Signal Output Hold Time (address standard)  
Address Output High-Impedance Time  
(Note 1)  
(Note 1)  
th(WR-DB)  
td(BCLK-ALE)  
th(BCLK-ALE)  
td(AD-ALE)  
th(ALE-AD)  
tdz(RD-AD)  
NOTES:  
18  
8
-2  
(Note 1)  
(Note 1)  
1. Values can be obtained from the following equations, according to BCLK frequency.  
10 9  
t
h(RD AD) =  
10  
10  
10  
10  
[ns]  
[ns]  
[ns]  
[ns]  
f
f
f
f
(BCLK) X 2  
10 9  
t
h(WR AD) =  
(BCLK) X 2  
10 9  
t
h(RD CS) =  
(BCLK) X 2  
10 9  
t
h(WR CS) =  
(BCLK) X 2  
109X m  
t
d(DB WR)  
h(WR DB)  
=
=
25  
[ns] (m=3 with 2 wait states and m=5 with 3 wait states)  
f
(BCLK) X 2  
10 9  
t
10 [ns]  
f(BCLK) X 2  
9
10  
t
d(AD ALE)  
h(ALE AD)  
=
=
20  
10  
[ns]  
[ns]  
f
(BCLK) X 2  
9
10  
t
f
(BCLK) X 2  
Page 53  
Rev. 1.41 Jan.31, 2006  
REJ03B0013-0141  
of 91  
 复制成功!