Bits 9, 3, and 2—Area 5 OE/WE Negate Address Delay (A5TEH2, A5TEH1, A5TEH0):
Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to
area 5.
Bit 9:
Bit 3:
Bit 2:
A5TEH2
A5TEH1
A5TEH0
Description
0
0
1
0
1
0
1
0
1
0
1
0
1
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
1
Bits 8, 1, and 0—Area 6 OE/WE Negate Address Delay (A6TEH2, A6TEH1, A6TEH0):
Specify the address hold delay time from OE/WE negation for the PCMCIA interface connected to
area 6.
Bit 8:
Bit 1:
Bit 0:
A6TEH2
A6TEH1
A6TEH0
Description
0
0
1
0
1
0
1
0
1
0
1
0
1
0.5-cycle delay
1.5-cycle delay
2.5-cycle delay
3.5-cycle delay
4.5-cycle delay
5.5-cycle delay
6.5-cycle delay
7.5-cycle delay
(Initial value)
1
Rev. 5.00, 09/03, page 251 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
