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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source  
clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified  
ratio. RTCOR must be set before setting CKS2-CKS0.  
Description  
Bit 5: CKS2  
Bit 4: CKS1  
Bit 3: CKS0  
Normal external bus clock  
Clock input disabled  
Bus clock (CKIO)/4  
CKIO/16  
0
0
0
1
0
1
0
1
0
1
1
0
1
CKIO/64  
1
CKIO/256  
CKIO/1024  
CKIO/2048  
CKIO/4096  
Bit 2—Refresh Count Overflow Flag (OVF): Indicates when the number of refresh requests  
indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit in RTCSR.  
Bit 2: OVF  
Description  
0
RFCR has not exceeded the count limit value set in LMTS  
Clearing condition: When 0 is written to OVF  
RFCR has exceeded the count limit value set in LMTS  
(Initial value)  
1
Setting condition: When the RFCR value has exceeded the count limit value  
*
set in LMTS  
Note: * Contents do not change when 1 is written to OVF.  
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Selects whether to suppress  
generation of interrupt requests by the OVF bit in RTCSR when OVF is set to 1.  
Bit 1: OVIE  
Description  
0
1
Interrupt request by OVF is disabled  
Interrupt request by OVF is enabled  
(Initial value)  
Rev. 5.00, 09/03, page 254 of 760  
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