Table 1.3 Pin Functions (cont)
Memory Interface
Pin
No.
Pin Name
I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
59
:(7/&$67/
O
D39–D32 select
signal
:(7
:(4
:(3
&$67
&$64
&$63
DQM4
DQM4
60
61
:(4/&$64/
O
O
D15–D8 select
signal
DQM1 :(4
DQM0
DQM1
:(3/&$63/
D7–D0 select
signal
DQM0
62
63
64
65
66
A17
A16
A15
VDD
VSS
O
O
O
Address
Address
Address
Power Internal VDD
Power Internal GND
(0 V)
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
A14
A13
VDDQ
VSSQ
A12
A11
A10
A9
O
O
Address
Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
O
O
O
O
Address
Address
Address
Address
Address
Address
Clock output
A8
A7
CKIO
VDDQ
VSSQ
A6
CKIO
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
O
O
O
Address
Address
Address
Address
Address
A5
A4
A3
A2
DRAK1
DMAC1 request
acknowledge
86
87
DRAK0
VDDQ
O
DMAC0 request
acknowledge
Power IO VDD (3.3 V)
Rev. 6.0, 07/02, page 25 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
