Table 1.3 Pin Functions (cont)
Memory Interface
Pin
No.
Pin Name
I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
168
SCK2/
05(6(7
I
SCIF clock/
manual reset
05(6(7 SCK2
SCK2
SCK2
SCK2
SCK2
169
170
VDD
Power Internal VDD
VSS
Power Internal GND
(0 V)
171
172
173
174
175
176
177
178
179
180
181
A18
O
O
O
O
O
O
Address
Address
Address
Address
Address
Address
A19
A20
A21
A22
A23
VDDQ
VSSQ
A24
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Address
Address
A25
MD3/&(5$ I/O
MD4/&(5% I/O
MD5/5$65 I/O
Mode/
PCMCIA-CE
MD3
MD4
MD5
&(5$
&(5%
182
183
184
185
Mode/
PCMCIA-CE
Mode/5$6
5$65
(DRAM)
DACK0
DACK1
O
O
O
DMAC0 bus
acknowledge
DMAC1 bus
acknowledge
186
187
188
189
190
191
192
A0
Address
VDDQ
VSSQ
A1
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
I
Address
Status
Status
STATUS0
STATUS1
MD6/
,2,649
Mode/,2,649
MD6
,2,649
(PCMCIA)
193
$6(%5./
I/O
Pin break/
acknowledge
(H-UDI)
BRKACK
Rev. 6.0, 07/02, page 29 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
