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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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17.3.3 Data Format  
Figure 17.3 shows the smart card interface data format. In reception in this mode, a parity check is  
carried out on each frame, and if an error is detected an error signal is sent back to the transmitting  
side to request retransmission of the data. If an error signal is detected during transmission, the  
same data is retransmitted.  
When there is no parity error  
Ds  
D0  
D1  
D2  
D3  
D4 D5  
D6  
D7 Dp  
Transmitting station output  
When a parity error occurs  
Ds  
D0  
D1  
D2  
D3  
D4 D5  
D6  
D7 Dp  
DE  
Transmitting station output  
Receiving  
station  
Ds:  
Start bit  
output  
D0–D7: Data bits  
Dp:  
DE:  
Parity bit  
Error signal  
Figure 17.3 Smart Card Interface Data Format  
The operation sequence is as follows.  
1. When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-  
up resistor.  
2. The transmitting station starts transmission of one frame of data. The data frame starts with a  
start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).  
3. With the smart card interface, the data line then returns to the high-impedance state. The data  
line is pulled high with a pull-up resistor.  
4. The receiving station carries out a parity check.  
If there is no parity error and the data is received normally, the receiving station waits for  
reception of the next data.  
Rev. 6.0, 07/02, page 712 of 986  
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