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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 2—Transmit End (TEND): The setting conditions for the TEND flag are as follows.  
Bit 2: TEND  
Description  
0
Transmission in progress  
[Clearing condition]  
When 0 is written to TDRE after reading TDRE = 1  
1
Transmission has been ended  
[Setting conditions]  
(Initial value)  
Power-on reset, manual reset, standby mode, or module standby  
When the TE bit in SCSCR1 is 0 and the FER/ERS bit is also 0  
When the GM bit in SCSMR1 is 0, and TDRE = 1 and FER/ERS = 0  
(normal transmission) 2.5 etu after transmission of a 1-byte serial  
character  
When the GM bit in SCSMR1 is 1, and TDRE = 1 and FER/ERS = 0  
(normal transmission) 1.0 etu after transmission of a 1-byte serial  
character  
etu: Elementary Time Unit (time for transfer for 1 bit)  
Bits 1 and 0—Reserved: Not used with the smart card interface.  
17.3  
Operation  
17.3.1 Overview  
The main functions of the smart card interface are as follows.  
One frame consists of 8-bit data plus a parity bit.  
In transmission, a guard time of at least 2 etu (elementary time unit: the time for transfer of one  
bit) is left between the end of the parity bit and the start of the next frame.  
If a parity error is detected during reception, a low error signal level is output for a 1-etu period  
10.5 etu after the start bit.  
If an error signal is detected during transmission, the same data is transmitted automatically  
after the elapse of 2 etu or longer.  
Only asynchronous communication is supported; there is no synchronous communication  
function.  
Rev. 6.0, 07/02, page 710 of 986  
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