Table 1.2 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
61
U3
%$&./
O
Bus
acknowledge/
bus request
%65(4
62
V3
%5(4/
I
Bus
request/bus
acknowledge
%6$&.
63
64
65
W2
Y2
D8
I/O
I/O
O
Data
Data
A8
D7
A7
W3
CKE
Clock output
enable
CKE
66
67
68
V5
U5
Y3
VDDQ
VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
:(8/&$68/ O
D47–D40
select signal
:(8
:(7
:(4
:(3
&$68
&$67
&$64
&$63
DQM5
DQM5
69
70
71
W4
Y4
:(7/&$67/ O
D39–D32
select signal
DQM4
DQM4
:(4/&$64/ O
D15–D8 select
signal
DQM1 :(4
DQM0
DQM1
W5
:(3/&$63/ O
D7–D0 select
signal
DQM0
72
73
74
75
76
77
78
Y5
V6
U6
W6
Y6
V7
U7
A17
O
Address
VDDQ
VSSQ
A16
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Address
Address
A15
VDD
VSS
Power Internal VDD
Power Internal GND
(0 V)
79
80
81
82
83
84
85
86
W7
Y7
V8
U8
V4
W8
Y8
W9
A14
O
O
Address
Address
A13
VDDQ
VSSQ
NC
Power IO VDD (3.3 V)
Power IO GND (0 V)
A12
O
O
O
Address
Address
Address
A11
A10
Rev. 6.0, 07/02, page 15 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
