1.4
Pin Functions
1.4.1
Pin Functions (256-Pin BGA)
Table 1.2 Pin Functions
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
1
2
3
4
5
6
7
8
9
10
B2
B1
C2
C1
D4
D3
D2
D1
E4
E3
5'<
5(6(7
&63
&64
&67
&68
&69
%6
I
Bus ready
Reset
5'<
5'<
5'<
I
5(6(7
O
O
O
O
O
O
Chip select 0
Chip select 1
Chip select 4
Chip select 5
Chip select 6
Bust start
&63
&64
&67
&68
&69
(%6)
&63
&64
&67
&68
&69
(%6)
&(4$
&(4%
(%6)
(%6)
(%6)
VSSQ
Power IO GND (0 V)
5'5
O
5'/&$66/
2(
&$6
2(
)5$0(
)5$0(
11
12
13
14
15
F3
F4
E2
E1
G3
VDDQ
VSSQ
D47
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O
I/O
Data/port
Data/port
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
D32
VDD
Power Internal VDD
(1.8 V)
16
G4
VSS
Power Internal GND
(0 V)
17
18
19
20
21
22
23
24
25
26
27
28
F2
F1
H3
H4
G2
G1
H2
H1
J3
D46
I/O
I/O
Data/port
Data/port
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
D33
VDDQ
VSSQ
D45
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O
I/O
I/O
I/O
Data/port
Data/port
Data/port
Data/port
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
D34
D44
D35
VDDQ
VSSQ
D43
Power IO VDD (3.3 V)
Power IO GND (0 V)
J4
J2
I/O
I/O
Data/port
Data/port
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
J1
D36
Rev. 6.0, 07/02, page 13 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
