1.2
Block Diagram
Figure 1.1 shows an internal block diagram of the SH7750 Series.
CPU
UBC
FPU
Lower 32-bit data
Lower 32-bit data
Cache and
TLB
I cache
ITLB
UTLB
O cache
controller
CPG
INTC
BSC
DMAC
SCI
(SCIF)
RTC
TMU
External
bus interface
26-bit
address
64-bit
data
BSC:
CPG:
Bus state controller
Clock pulse generator
UTLB: Unified TLB (translation lookaside buffer)
RTC:
SCI:
Realtime clock
Serial communication interface
DMAC: Direct memory access controller
FPU: Floating-point unit
INTC: Interrupt controller
ITLB: Instruction TLB (translation lookaside buffer)
SCIF: Serial communication interface with FIFO
TMU: Timer unit
UBC: User break controller
Figure 1.1 Block Diagram of SH7750 Series Functions
Rev. 6.0, 07/02, page 9 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
