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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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1. Transfer requests are issued simultaneously for channels 0 and 3.  
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed  
first (channel 3 is on transfer standby).  
3. A transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on  
transfer standby).  
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.  
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is  
started (channel 3 is on transfer standby).  
6. At the end of the channel 1 transfer, channel 1 shifts to the lowest priority level.  
7. The channel 3 transfer is started.  
8. At the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered,  
giving channel 3 the lowest priority.  
Transfer request  
Channel  
waiting  
DMAC operation  
Channel priority  
order  
1. Issued for channels 0  
and 3  
2. Start of channel 0  
transfer  
0 > 1 > 2 > 3  
3. Issued for channel 1  
3
Change of  
priority order  
1 > 2 > 3 > 0  
4. End of channel 0  
transfer  
1, 3  
5. Start of channel 1  
transfer  
Change of  
priority order  
2 > 3 > 0 > 1  
6. End of channel 1  
transfer  
3
7. Start of channel 3  
transfer  
None  
Change of  
priority order  
0 > 1 > 2 > 3  
8. End of channel 3  
transfer  
Figure 14.4 Example of Changes in Priority Order in Round Robin Mode  
Rev. 6.0, 07/02, page 517 of 986  
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