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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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2. If input capture interrupt acceptance is set for multiple channels and DE = 1 for each  
channel, processing will be executed on the highest-priority channel in response to a  
single input capture interrupt.  
3. A DMA transfer request by means of an input capture interrupt can be canceled by  
setting TCR2.ICPE1 = 0 and ICPE0 = 0 in the TMU.  
*
External memory or memory-mapped external device  
To output a transfer request from an on-chip peripheral module, set the DMA transfer request  
enable bit for that module and output a transfer request signal.  
For details, see sections 12, Timer Unit (TMU), 15, Serial Communication Interface (SCI), and  
16, Serial Communication Interface with FIFO (SCIF).  
When a DMA transfer corresponding to a transfer request signal from an on-chip peripheral  
module shown in table 14.5 is carried out, the signal is discontinued automatically. This occurs  
every transfer in cycle steal mode, and in the last transfer in burst mode.  
14.3.3 Channel Priorities  
If the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel  
according to a predetermined priority system, either in a fixed mode or round robin mode. The  
mode is selected with priority bits PR1 and PR0 in the DMA operation register (DMAOR).  
Fixed Mode: In this mode, the relative channel priorities remain fixed. The following priority  
orders are available in fixed mode:  
CH0 > CH1 > CH2 > CH3  
CH0 > CH2 > CH3 > CH1  
CH2 > CH0 > CH1 > CH3  
The priority order is selected with bits PR1 and PR0 in DMAOR.  
Round Robin Mode: In round robin mode, each time the transfer of one transfer unit (byte, word,  
longword, quadword, or 32 bytes) ends on a given channel, that channel is assigned the lowest  
priority level. This is illustrated in figure 14.3. The order of priority in round robin mode  
immediately after a reset is CH0 > CH1 > CH2 > CH3.  
Note: In round robin mode, if no transfer request is accepted for any channel during DMA  
transfer, the priority order becomes CH0 > CH1 > CH2 > CH3.  
Rev. 6.0, 07/02, page 515 of 986  
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